Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same

ABSTRACT

A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

RELATED APPLICATION

This application is a divisional of copending U.S. application Ser. No.10/639,541, filed Aug. 12, 2003, which is a divisional of U.S.application Ser. No. 09/861,697, filed on May 21, 2001, now U.S. Pat.No. 6,626,968, the contents of which are incorporated herein in theirentirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a slurry composition for a chemicalmechanical polishing process and a method of manufacturing asemiconductor device using the same, and, more particularly, to a slurryfor a chemical mechanical polishing (hereinafter referred to as “CMP”)process that results in a high selectivity ratio to polysilicon and to amethod of planarizing the surface of a semiconductor device using thesame.

2. Description of the Related Art

The high performance and high integration requirements of modernsemiconductor devices demand a multilayer interconnection structure.This multilayer interconnection structure is typically made byperforming the sequential steps of film forming/layer depositionfollowed by an etch process of conductive layers and insulating layers,and repeating these steps several times. Predetermined patterns requiredfor each layer are formed, and then a surface planarization step isperformed so that a lithographic process may be easily performed beforeanother pattern is formed.

This planarization step is classified into local planarization andglobal planarization. The ultimate object of planarization technology isto realize global planarization. Techniques for this globalplanarization typically include the steps of forming a coating of resin,such as polyimide, followed by an etch-back step, a reflow, and a CMPfor the metallic and insulating layers.

A wafer on which a planarization process will be performed is mounted ona rotatory plate, and the surface of the wafer is made to contact apolishing pad. After this, CMP is carried out by rotating the rotatoryplate and the polishing pad while providing a supply of slurry betweenthe wafer surface and the polishing pad. In other words, a CMP processis a combination of a chemical action of a slurry, comprising a chemicalsolution and abrasive grains, and the mechanical action of a polisher.The slurry is supplied between the wafer surface and the polishing pad,and mechanical friction is generated due to the abrasive grains in theslurry and the surface of the pad. As a result of the mechanicaleffects, the wafer surface is polished. At the same time, part of thewafer surface is removed by the chemical reaction of the chemicalcomponents in the slurry with at least portions of the wafer surface.

In general, various kinds of CMP slurries are used depending on thecharacteristics of the wafer surface materials to be removed. Inparticular, in a case where a polysilicon layer and a silicon oxidelayer are being polished by a CMP method employing a silica-based slurryusing silica (SiO₂) as an abrasive grain, over a given period abouttwice as much of the polysilicon layer will be removed than the amountof the silicon oxide layer removed. Thus, it can be said that theselectivity ratio of the polysilicon layer to the silicon oxide layerfor this CMP process is about 0.5:1. It is therefore difficult orimpossible to use a polysilicon layer as a polishing stopping layer whena CMP process is carried out in a specific step of a semiconductordevice manufacturing process when using a conventional silica-basedslurry. However, for some applications it may be inevitable to carry outsuch a CMP process despite the problem of the selectivity ratio betweena polysilicon layer and a silicon oxide layer in a manufacturing processof a semiconductor device. Alternatively, it may be desirable to use apolysilicon layer as a polishing stopping layer in several steps, notonly in a single specific step. Accordingly, it would be desirable todevelop a new slurry composition which can be useful in carrying outthese types of CMP processes.

OBJECTS OF THE INVENTION

To solve the above problems, it is a general object of the presentinvention to provide a new slurry composition suitable for a chemicalmechanical polishing (CMP) process in which an exposed surface of amaterial to be polished has the property of hydrophilicity with respectto the slurry.

It is another object of the present invention to provide a method ofmanufacturing a semiconductor device in which there is a material layerbetween patterns, and wherein the exposed surface of that material layerhas the property of hydrophobicity with respect to the slurry, such thatthe exposed surface can be globally planarized by a CMP process.

It is still another object of the present invention to provide a methodof manufacturing a semiconductor device where global planarization canbe carried out with a CMP process using a material layer as a polishingstopping layer wherein the exposed surface of that layer has theproperty of hydrophobicity with respect to the slurry.

SUMMARY OF THE INVENTION

Accordingly, to achieve the above objects, there is provided a newslurry composition for a chemical mechanical polishing (CMP) processconsisting essentially of water, abrasive grains, and a polymer additivehaving both hydrophilic and hydrophobic functional groups. The slurry isused for polishing a hydrophilic material, the surface of which isexposed to the slurry in a CMP process. The slurry may further comprisea surfactant and a pH control agent containing acid or base. The polymeradditive is at least one member selected from the group consisting ofpoly vinyl methyl ether (PVME), poly ethylene glycol (PEG), polyoxyethylene 23 lauryl ether (POLE), poly propanoic acid (PPA), polyacrylic acid (PAA), and poly ether glycol bis ether (PEGBE).

To achieve the above-described objects, there is provided a method ofmanufacturing a semiconductor device according to a first embodiment ofthe present invention. In this first embodiment, a first material layerpattern is formed on a lower layer. The surface of the first materiallayer is then exposed to the slurry according to the present inventionand exhibits hydrophobicity during the CMP process. A second materiallayer is thereafter formed on the entire resultant structure on whichthe first material layer pattern was formed. The surface of the secondmaterial layer is then exposed to the slurry according to the presentinvention and exhibits hydrophilicity during the CMP process. A CMPprocess is performed on the second material layer in order to expose atleast a portion of the surface of the first material layer using aslurry comprising water, abrasive grains, and polymer additive havingboth hydrophilic and hydrophobic functional groups. Preferably, in thisembodiment of the invention, the first material layer is formed ofpolysilicon and the second material layer is formed of silicon oxide.

To further achieve the above-described objects, there is provided amethod of manufacturing a semiconductor device according to a secondembodiment of the present invention. In this second embodiment, an etchmask pattern including a first material layer is formed on asemiconductor substrate. The surface of the etch mask pattern is thenexposed to a slurry according to the present invention and exhibitshydrophobicity during the CMP process. A trench is formed to apredetermined depth in the semiconductor substrate using the etch maskpattern as a guide. A second material layer having insularity isthereafter formed on the entire resultant structure where the trench wasformed. The surface of the second material layer is then exposed to theslurry according to the present invention and exhibits hydrophilicityduring the CMP process. A CMP process is performed on the secondmaterial layer in order to expose at least a portion of the surface ofthe first material layer of the etch mask pattern using the slurrycomprising water, abrasive grains, and polymer additive having bothhydrophilic and hydrophobic functional groups. The remaining firstmaterial layer is then removed.

An anti-reflective layer is further formed on the first material layerof the etch mask pattern, and a first oxide layer is formed between thesemiconductor substrate and the first material layer of the etch maskpattern. A thermal oxide layer is formed on the exposed surface of thetrench after the formation of the trench. After the remaining firstmaterial layer is removed, a sacrificial oxide layer may be formed onthe semiconductor substrate.

To further achieve the above-described objects, there is provided amethod of manufacturing a semiconductor device according to a thirdembodiment of the present invention. In this third embodiment, an upperelectrode of a capacitor, including a first material layer havingconductivity, is formed on an interlayer insulating layer of asemiconductor substrate. The surface of the first material layer is thenexposed to a slurry according to the present invention and exhibitshydrophobicity during the CMP process. A second material layer isthereafter formed on the entire resultant structure where the upperelectrode was formed. The surface of the second material layer is thenexposed to the slurry according to the present invention and exhibitshydrophilicity during the CMP process. A CMP process is performed on thesecond material layer in order to expose the first material layer usingthe slurry containing water, abrasive grains, and polymer additivehaving both hydrophilic and hydrophobic functional groups. A thirdmaterial layer having insularity is thereafter formed on the entireresultant structure. The surface of the third material layer is exposedto the slurry according to the present invention and exhibitshydrophilicity during the CMP process. A CMP process is performed atleast one time on the third material layer in order to expose thesurface of the first material layer using the slurry comprising water,abrasive grains, and polymer additive having both hydrophilic andhydrophobic functional groups. The third material layer may be reflowedunder heat after forming the third material layer.

According to the present invention, a CMP is performed on a hydrophobicmaterial, a surface of which is exposed to a slurry according to thepresent invention during a CMP process causing the surface to bepolished. The slurry contains a polymer additive having both ahydrophobic functional group and a hydrophilic functional group. Ahydrophilic material layer which is deposited on the surface as apolishing stopping layer, is also exposed to the slurry during a CMPprocess. Polymer is selectively adsorbed only on the surface of thehydrophobic material layer. As a result, a passivation layer is formedto protect the surface of the hydrophobic material layer from beingetched. Meanwhile, the hydrophilic material deposited on the surface tobe polished does not react with polymer. Thus, it is easy to remove thehydrophilic material from the surface to be polished.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objectives and advantages of the present invention will becomemore apparent by describing in detail preferred embodiments thereof withreference to the attached drawings in which:

FIG. 1 is a drawing for explaining the properties of hydrophobicity andhydrophilicity of a surface exposed to a slurry in a chemical mechanicalpolishing (CMP) process according to an embodiment of the presentinvention.

FIG. 2 is a drawing for explaining how a hydrophobic surface exposed toa slurry during a CMP process according to an embodiment of the presentinvention is protected.

FIG. 3 is a graph illustrating removal rates and selectivity ratiosbased on a change in hydrogen ion (pH) values of a slurry according toan embodiment of the present invention.

FIGS. 4 and 5 are cross-sectional views for describing the steps ofmanufacturing a semiconductor device, including at least a CMP step,according to a first embodiment of the present invention.

FIGS. 6 through 10 are cross-sectional views for describing the steps ofmanufacturing a semiconductor device wherein a trench isolationstructure is formed by a CMP process according to a second embodiment ofthe present invention.

FIGS. 11 through 13 are cross-sectional views for describing the stepsof manufacturing a semiconductor device wherein planarization is carriedout by a CMP process according to a third embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter embodiments of the present invention will be described indetail with reference to the attached drawings. However, it will beunderstood that the embodiments of the present invention can be modifiedinto various other forms, and the scope of the present invention shouldnot be interpreted as being restricted to the specifically describedembodiments. The several specific embodiments described herein areprovided to more completely explain the present invention to thoseskilled in the art. In the drawings, the thicknesses of layers orregions are exaggerated for clarity, and like reference numerals denotethe same members in different drawings. Also, when it is written that alayer is formed “on” another layer or a substrate, it is meant that thelayer can be formed directly on the other layer or the substrate, oralternatively other layers can intervene therebetween.

The semiconductor device manufacturing process of the present inventionincludes chemical mechanical polishing (CMP), which is a planarizationtechnology. CMP is a technique for globally and uniformly planarizing awafer surface containing heterogeneous substances. In planarizing thewafer surface by CMP, a uniformly flat surface can be achieved in theglobal planarization process. In this case, not only are materialremoval rates irregular, depending on substances, but also a multilayerstructure of a semiconductor device is thin film and thus it isdifficult or impossible to control the material removal ratesaccurately. In accordance with the present invention, improved globalplanarization can be accomplished by utilizing the exposed surface of apolishing stopping layer wherein the polishing layer has a lowermaterial removal rate than the material to be polished duringplanarization.

Thus, the CMP process according to the present invention is performedusing one material, the surface of which is exposed to a slurry in a CMPprocess and which exhibits hydrophilicity, as a material to be polished,and using another material, the surface of which is exposed to a slurryin a CMP process and which exhibits hydrophobicity, as a polishingstopping layer. Hereinafter, the slurry applied to the CMP process andthe steps of manufacturing a semiconductor device using the same will bedescribed in detail.

1. Improved Slurry Composition

A slurry useful for carrying out a CMP process is a liquid compositionwhich generally contains water and abrasive grains. In this embodiment,a commonly used slurry (model name SS25 developed by American CabotCorporation) for polishing an oxide layer is used. Here, the liquid isdeionized water and the abrasive grains are silica-based abrasivegrains. However, other common abrasive grains, such as alumina (Al₂O₃),ceria (CeO₂), and magania (Mn₂O₃), may also be used. The size and amountof the abrasive grains dispersed in the slurry have a large effect onpolishing efficiency. Thus, in this embodiment, the amount of theabrasive grains is preferably about 25% by weight or less, for exampleabout 1 to 25% by weight. For example, silica (SiO₂) is preferably usedwithin the range of about 5 to 12.5% by weight, and ceria is preferablyused within the range of about 1 to 10% by weight.

A surfactant for activating the interface between the slurry and thematerial to be polished, and/or an agent for controlling the pH of theslurry may also be added to the slurry. In other words, a base such aspotassium hydroxide (KOH) or an acid such as sulfuric acid (H₂SO₄),nitric acid (HNO₃), hydrochloric acid (HCl), or phosphoric acid (H₃PO₄)may be added in small, controlled amounts to the slurry sufficient toadjust the slurry pH to within the range of about 7 to 11.

Meanwhile, one or a mixture of polymers having both a hydrophilicfunctional group and a hydrophobic functional group is further added tothe slurry composition of the present invention. Polar materialscontaining oxygen, nitrogen, and sulfur, such as an —OH group, a —COOHgroup, an —NH₂ group, or an —SO₃H group, are hydrophilic. On the otherhand, hydrocarbons of an aliphatic group and an aromatic group notincluding these polar functional groups are hydrophobic. The addedpolymer having a hydrophilic functional group and a hydrophobicfunctional group may include poly vinyl methyl ether (PVME), polyethylene glycol (PEG), poly oxyethylene 23 lauryl ether (POLE), polypropanoic acid (PPA), poly acrylic acid (PAA), and poly ether glycol bisether (PEGBE), and mixtures thereof. Among these polymers, only one mayadded or two or more may be added. In this embodiment, about 0.001 to 5%by weight of polymer or polymer mixture is added to the slurry.

FIG. 1 is a drawing for describing the hydrophilic and hydrophobicsurfaces which are exposed to a slurry in a CMP process according to thepresent invention. FIG. 2 is a drawing for describing the steps offorming a passivation layer on a hydrophobic surface which is to beexposed to a slurry in a CMP process according to the present invention.

Referring to FIG. 1, there are provided a first hydrophobic materiallayer 10 and, adjacent thereto, a second hydrophilic material layer 20,the surfaces of which are to be exposed to a slurry in a CMP process. Incontrast with bulk material, surface oxides or surface pollutants areeasily adsorbed on the surfaces of many materials to stabilize theiractive properties. Thus, in FIG. 1, a portion of the surface layer orthe bulk layer is removed from the surfaces of the first and secondmaterial layers 10 and 20 by CMP processes. As a result, a materiallayer identical in composition to the bulk layer and free of surfaceoxides or surface pollutants is left on the surfaces of the first andsecond material layers 10 and 20. These surfaces are a newly-formedsurfaces which are highly reactive and thus react with the slurrycomposition with which they are in contact, thereby generating andstabilizing new surfaces.

In a case where a CMP process is performed using a slurry containingwater, the newly-formed surface of the first material layer 10 combineswith hydrogen ions from the water and then exhibits hydrophobicity.Correspondingly, the newly-formed surface of the second material layer20 combines with hydroxyl groups from water and then exhibitshydrophilicity. For example; under these conditions, a polysilicon layer10 would form a hydrophobic surface, whereas a silicon oxide layer 20would form a hydrophilic surface.

With reference to FIG. 2, in a case where a CMP process is to beperformed using a slurry according to the present invention, polymerhaving both hydrophilic and hydrophobic functional groups is added tothe slurry as previously described. Thus, polymer is selectivelyadsorbed only on the surface of the first material layer 10 havinghydrophobicity; and, as a result, a passivation layer 12 is formedthereon. The polymer passivation layer 12 subsequently restrains thechemical reaction of the first material layer 10 with the slurry duringa CMP process. As a result, the removal rate of the first material layer10 during a CMP process drops sharply, while the removal rate of thesecond material layer 20, which does not react with the added polymer,is maintained. Thus, the selectivity ratio of the first material layer10 to the second material layer 20 is significantly increased inaccordance with the present invention.

Table 1 below shows the results of a CMP process on a silicon oxidelayer and a polysilicon layer using a slurry according to the presentinvention which includes poly vinyl methyl ether (PVME). TABLE 1 Amountof PVME added 0.01% 0.1% by wt by wt 1% by wt 0% by wt Removal Rate ofOxide 2556 2030 1926 2677 Layer (Å/min) Removal Rate of Polysilicon 408278 248 3972 Layer (Å/min) Selectivity Ratio 6.3 7.3 7.8 0.7

As shown in Table 1, in a case where PVME is not added to the slurry,the removal rate of the polysilicon layer during a CMP process is muchgreater than that of the oxide layer, and thus the selectivity ratio isonly 0.7, which is not acceptable. In a case where PVME is added to theslurry, however, the selectivity ratio of the oxide layer to thepolysilicon layer is considerably increased to between 6.3 and 7.8(depending on the amount of PVME added), which yields a highlyacceptable result. Also, it is seen that the selectivity ratio increasessomewhat with an increase in the addition of PVME from 0.01% by weightto 1% by weight.

FIG. 3 is a graph for showing how the removal rate and the selectivityratio of the oxide layer and the polysilicon layer change based on achange in pH by adding sulfuric acid (H₂SO₄) to a slurry containing 1%by weight PVME. FIG. 3 shows that the selectivity ratio generallyincreases along with a decrease in the pH of the slurry. Although theremoval rate of polysilicon varies little over pH ranges of about 7.5 to11.5, FIG. 3 shows that the removal rate of the oxide layer decreasessignificantly at lower pH values resulting in higher selectivity ratios.When the pH is 8, the selectivity ratio of the polysilicon layer to theoxide layer is 25:1.

Table 2 below shows the results of carrying out a CMP process on asurface comprising adjacent silicon oxide and polysilicon layers using aslurry to which poly ethylene glycol (PEG) has been added. TABLE 2Amount of PEG added 0.01% by wt 0.1% by wt 1% by wt Removal Rate ofOxide Layer 2194 2336 2183 (Å/min) Removal Rate of Polysilicon 777 683580 Layer (Å/min) Selectivity Ratio 2.8 3.4 3.8

From Table 2, it is seen that the selectivity ratio of the polysiliconlayer to the oxide layer increases with an increase in the amount of PEGadded to the slurry.

Table 3 below shows the results of carrying out a CMP process on asurface comprising adjacent silicon oxide and polysilicon layers using aslurry to which poly ether glycol bis ether (PEGBE) has been added.TABLE 3 Amount of PEGBE added 0.01% by wt 0.1% by wt 1% by wt RemovalRate of Oxide 2361 2369 2389 Layer (Å/min) Removal Rate of Polysilicon1477 1046 776 Layer (Å/min) Selectivity Ratio 1.6 2.3 3.1

From Table 3, it is seen that the selectivity ratio of the polysiliconlayer to the oxide layer increases with an increase in the amount ofPEGBE added to the slurry.

Table 4 below shows the results of carrying out a CMP process on asurface comprising adjacent silicon oxide and polysilicon oxide layersusing a slurry to which poly oxyethylene23 lauryl ether (POLE) (productname Brij35) has been added. TABLE 4 Amount of POLE added 0.01% by wt0.1% by wt 0.5% by wt Removal Rate of Oxide 2621 2520 2554 Layer (Å/min)Removal Rate of Polysilicon 662 633 830 Layer (Å/min) Selectivity Ratio4.0 4.0 4.0

From Table 4, it is seen that even a small addition of 0.01% by weightof POLE to the slurry results in a significant increase to 4.0 of theselectivity ratio of the polysilicon layer to the oxide layer and towell above the 0.7 ratio seen with no polymer addition (see Table 1).Further increases in the amount of POLE added to the slurry, however,did not seem to further improve the selectivity ratio.

As described above, compared with a conventional slurry without anyadded polymer, using the slurry of the present invention (containingpolymer having both hydrophobic and hydrophilic functional groups)results in substantially the same removal rate of an oxide layer at thesame time that the removal rate of a polysilicon layer is substantiallydecreased. As a result, the selectivity ratio is greatly improvedthereby making it possible to utilize CMP processes in semiconductormanufacturing operations where, in the past, CMP processes were greatlylimited.

2. Manufacturing Processes of a Semiconductor Device Using a Slurry ofthe Present Invention

Embodiment 1

FIGS. 4 and 5 are cross-sectional views for describing semiconductormanufacturing processes which include a CMP process using apolymer-containing slurry according to a first embodiment of the presentinvention. Referring to FIG. 4, a first material layer pattern 32 isformed on a portion of a lower layer 30. The lower layer 30, which cansupport the first material layer pattern 32 mechanically, may be asemiconductor substrate, or a specific insulating material layer, or ametallic interconnection layer on a semiconductor substrate. The firstmaterial layer pattern 32, made, e.g., of polysilicon, comprises asurface which is to be exposed to a slurry in a CMP process and whichexhibits hydrophobicity. The first material layer pattern 32 may beformed by a common photolithographic etching process using photoresist.Also, an anti-reflective layer, such as a silicon oxynitride (SiON)layer, may be further formed on the first material layer pattern 32before the first material layer pattern 32 is coated with photoresist(not shown).

Meanwhile, a trench may be formed in the lower layer 30 by etching aportion of the lower layer 30 with the formation of the first materiallayer pattern 32. Also, an intermediate material layer (not shown) maybe further formed between the lower layer 30 and the first materiallayer pattern 32, and then that intermediate material layer may bepatterned similar to the first material layer pattern 32.

A second material layer 34 is then formed on the entire resultantstructure such that a step difference is made due to the formation ofthe first material layer pattern 32 on a portion of layer 30. The secondmaterial layer 34, made, e.g., of silicon oxide, comprises a surfacewhich is to be exposed to a slurry in a CMP process and which exhibitshydrophilicity. In general, an oxide layer denotes a silicon oxide layerand may include a variety of oxide layers, e.g., a borophosphoroussilicate glass (BPSG) layer, an undoped silicate glass (USG) layer, aspin on glass (SOG) layer, a high density plasma (HDP) oxide layer, aplasma enhanced tera-ethyl ortho silicate glass (PETEOS) layer, and athermal oxide layer. Also, the silicon oxide layer can be formed by avariety of known techniques, e.g., by a thermal oxidation method, by achemical vapor deposition (CVD) method, or by a physical vapordeposition (PVD) method. It is preferable that the second material layer34 be thicker than the first material layer pattern 32 in order toovercome the step difference due to the first material layer pattern 32and to facilitate global planarization. However, in a case where thefirst material layer pattern 32 is very high, the second material layer34 may get thicker by stacking the same upon itself several times.

FIG. 5 shows the structure of FIG. 4 in which the surface of the secondmaterial layer 34 has been planarized by a CMP process to expose thesurface of the first material layer pattern 32 using the previouslymentioned slurry according to the present invention. The slurry containsliquid, abrasive grains, and a polymer additive having both hydrophilicand hydrophobic functional groups. During the CMP process, the polymeris selectively adsorbed only on the portion of the surface comprisingthe first material layer pattern 32 which is exposed to the slurry andwhich exhibits hydrophobicity due to the hydrophobic functional group ofthe polymer. As a result, the selectivity ratio of the first materiallayer pattern 32 to the second material layer 34 is increased. Thus, thesurface of the first material layer pattern 32 serves as a CMP stoppinglayer, which improves the surface uniformity and the results of asubsequent photolithographic process margin carried out after the CMPprocess is completed.

Embodiment 2

FIGS. 6 through 10 show cross-sectional views for describingsemiconductor manufacturing processes which include a CMP process and atrench isolation process using a polymer-containing slurry according toa second embodiment of the present invention. Referring to FIG. 6, afirst oxide layer 42, a first material layer 44, and an anti-reflectivelayer 46 are sequentially formed on a semiconductor substrate 40. Thefirst material layer 44, the surface of which is to be exposed to theslurry in a CMP process and which exhibits hydrophobicity, is formed ofpolysilicon to a thickness of about 1000 to 3000 Å. The anti-reflectivelayer 46 is formed of silicon oxynitride (SiON). The anti-reflectivelayer 46 is coated with a photoresist 48, and then a photoresist patternis formed by a common photolithographic process to delimit a trench areato be formed by a subsequent process. An etch mask pattern is formed byetching the anti-reflective layer 46 and the first material layer 44 insequence using the photoresist pattern as an etch mask. In thisembodiment, the first oxide layer 42 underneath the first material layer44 may be etched along with the first material layer 44.

With reference to FIG. 7, the remaining photoresist pattern on thestructure shown in FIG. 6 is removed by a common method such as ashing.Next, a trench 50 is formed in the semiconductor substrate 40 to apredetermined depth by etching the first oxide layer 42 and thesemiconductor substrate 40 underneath using the anti-reflective layer 46and the material layer 44 as an etch mask. The trench 50 may be formed,for example, by anisotropic etching using chlorine and hydrogen bromideas etch gases, to a depth appropriate for electrical insulation ofadjacent semiconductor devices. Impurity ions (not shown) of the sameconductive type as those in the semiconductor substrate 40 may befurther implanted into a lower portion of the trench 50 as a channelstopper after the trench 50 is formed.

Referring now to FIG. 8, a thermal oxide layer 52 is formed on thebottom face and the sidewalls of the trench 50 as shown in FIG. 7 byheating the semiconductor substrate 40 in which the trench 50 is formed.The thermal oxide layer 52 removes defects generated in thesemiconductor substrate 40 during the anisotropic etching for formingthe trench 50, prevents current leakage through the surface of thetrench 50 by keeping the exposed surface of the semiconductor substrate40 in a stable bond state (Si—O₂ bond), and also prevents theconcentration of stress by somewhat rounding the corners of the bottomof the trench. As shown in FIG. 8, the thermal oxide layer 52 is formedalong the exposed sidewalls of the first oxide layer 42 and the firstmaterial layer 44 made of polysilicon, as well as at the bottom andsidewalls of the trench 50. A second material layer 54 having insularityis formed on the entire resultant structure where the thermal oxidelayer 52 is formed resulting in burying the trench 50. The secondmaterial layer 54, the surface of which is to be exposed to the slurryin a CMP process and which exhibits hydrophilicity, can be made ofsilicon oxide such as BPSG, USG, SOG, HDP, PETEOS, or thermal oxide. Thesilicon oxide layer 54 can be formed by a variety of known techniques,such as a thermal oxidation method, a CVD method, or a PVD method. Thesecond material layer 54 is thicker than the depth of the trench 50 tobury the trench 50 and planarize the surface.

With reference to FIG. 9, the surfaces of the second material layer 54and the anti-reflective layer 46 as seen in FIG. 8 are now removed andplanarized by a CMP process using the previously mentioned slurry of thepresent invention in order to expose the surface of the first materiallayer 54 along the top of trench 50. In carrying out the CMP process,polymer additive having both hydrophobic and hydrophilic functionalgroups is added to the slurry as previously described.

Referring now to FIG. 10, the remaining first material layer pattern 44as shown in FIG. 9 is removed with a suitable etch solution for removingthe first material layer 44. The first oxide layer 42 remaining on thesemiconductor substrate 40 is then also removed. Next, the secondmaterial layer 54 having insularity is filled in and above the trench 52and an isolation area, and the surface of the resultant structure isplanarized. Meanwhile, a sacrificial oxidation process may be furtherperformed after the first oxide layer 42 is removed. A sacrificial oxidelayer is grown to a thickness of about 50 to 200 Å on the exposedsemiconductor substrate 40 and then is removed with an oxide agent suchas buffered oxide etchant (BOE) and hydrofluoric acid (HF) in asacrificial oxidation process. This sacrificial process helps toeliminate defects or to repair damage generated on the substrate surfaceby the previously-mentioned CMP process. Also, after the sacrificialoxide layer is grown, ions for the formation of well, a channel stopper,or the control of threshold voltage may be implanted into thesemiconductor substrate 40.

In this embodiment, the slurry used in the CMP process contains liquid,abrasive grains, and polymer additive having both hydrophilic andhydrophobic functional groups. During the CMP process, polymer isadsorbed on the surface of the first material layer 44 which is exposedto the slurry because of the hydrophobic functional group of thepolymer. As a result, the selectivity ratio of the first material layer44 to the second material layer 54 (see FIG. 8) is increased. Thus, thefirst material layer 44 serves as a CMP stopping layer, which improvesthe surface uniformity following the CMP process.

Embodiment 3

FIGS. 11 through 13 are cross-sectional views for describingsemiconductor manufacturing processes which include a planarizationprocess using CMP according to a third embodiment of the presentinvention.

FIG. 11 shows a capacitor formed on a semiconductor substrate. Themanufacturing process thereof is as follows. A contact hole is formed ina interlayer insulating layer 60 on a semiconductor substrate (notshown). Next, a lower electrode 62 is formed by depositing on the entiresemiconductor substrate and patterning a material for a lower electrodeof the capacitor. Next, a dielectric layer 64 is formed on the exposedsurface of the lower electrode 62. An upper electrode 66 is then formedby depositing and patterning a first material layer for an upperelectrode of the capacitor on the entire semiconductor substrate. Theupper electrode 66, the surface of which is to be exposed to the slurryin a CMP process and which exhibits hydrophobicity, is made of aconductive material, e.g., polysilicon. A second material layer 68having insularity is then formed on the entire resultant structure toreduce the surface step difference between a memory cell area where theupper electrode 66 is formed (left portion of FIG. 11) and a peripheralarea where a pattern such as the upper electrode 66 is not formed (rightportion of FIG. 11). The second material layer 68, the surface of whichis to be exposed to the slurry in a CMP process and which exhibitshydrophilicity, is made of BPSG. However, the second material layer 68may alternatively be made of any of the members of the group consistingof PSG, PETEOS, and USG instead of BPSG. It is preferable that thesecond material layer 68 have a reflow property which is advantageous toa surface planarization. Preferably, the second material layer 68 isdeposited to a depth that is thicker than the height from the surface ofthe interlayer insulating layer 60 to the top surface of upper electrode66 in order to overcome the step difference made by the upper electrodepattern 66 and to facilitate planarizing the surface. However, in a casewhere the upper electrode 66 is very high, the second material layer 68can be made thicker by stacking the same upon itself several times.

Referring to FIG. 12, a CMP process is now performed on the structureshown in FIG. 11 using the previously mentioned slurry of the presentinvention to planarize the second material layer 68 so that the uppersurface of the upper electrode 66 is exposed. In a case where CMP isperformed using a slurry containing dispersed silica-based abrasivegrains to which 1% by weight of PVME is added, the removal rate of apolysilicon layer (e.g., electrode 66) is about 210 Å/min, while theremoval rate of an unannealed BPSG layer is about 8786 Å/min. Forcomparison, the removal rate of an annealed BPSG layer is about 5374Å/min, and the removal rate of a PETEOS layer is about 1250 Å/min. Thus,the selectivity ratios of these three material layers which may compriselayer 68 relative to the polysilicon layer 66 are respectively 42:1,27:1, and 6:1. Alternatively, in a case where the polysilicon layer 66is annealed, the removal rate thereof increases to about 480 Å/min,thereby reducing the selectivity ratio considerably. Thus, it ispreferable that a reflow process requiring a heat treatment not beperformed for the second material layer 68 prior to carrying out the CMPprocess.

The CMP process is preferably performed at a low pressure, e.g., at apressure of about 2 to 5 psi to minimize possible damage to the edges ofthe upper electrode 66.

With reference now to FIG. 13, a third material layer 70 havinginsularity is formed on the entire resultant structure after it has beenplanarized to expose the surface of the upper electrode 66 as shown inFIG. 12. In a case where the upper surface of the upper electrode 66 isnot fully planarized by only one CMP process due to the very high heightthereof, the CMP process can be repeated several times using the slurryof the present invention so that the upper surface of the upperelectrode 66 will be exposed after the third material layer 70 isformed. It is preferable that the third material layer 70 be comprisedof a dielectric material, the surface of which is to be exposed to theslurry and which exhibits hydrophilicity, and more preferably, thatlayer 70 be comprised of the same material as the second material layer68. Then, a reflow process is performed at a temperature of about 850°C. The reflow process is a global planarization technique which utilizesthe mobility of a heated material layer to help effect planarization.The initial surface (labeled “L1” in FIG. 13) of the third materiallayer 70 is globally planarized to some extent by carrying out a reflowprocess resulting in a more planarized surface (labeled “L2” in FIG. 13)for layer 70.

The slurry used in this embodiment also contains polymer additive havingboth hydrophilic and hydrophobic functional groups in accordance withthe present invention. Thus, during a CMP process, polymer is adsorbedon the surface of the upper electrode 66 which is to be exposed to theslurry and which exhibits hydrophobicity due to the hydrophobicfunctional group of the polymer. As a result, the selectivity ratio ofthe upper electrode 66 relative to the second material layer 68 isincreased. Accordingly, the upper electrode 66 serves as a CMP stoppinglayer, which improves the surface uniformity following the CMP processand facilitates a subsequent photolithographic etch process margin.

As described above, according to the present invention, polymer havingboth hydrophilic and hydrophobic functional groups is added to a CMPslurry. Thus, the polymer is adsorbed on a material layer, the surfaceof which is to be exposed to the slurry and which exhibitshydrophobicity. Since the material layer serves as a CMP passivationlayer, it is useful as a CMP stopping layer. Also, in a case where theslurry of the present invention is used for carrying out a CMP processon a material layer having a hydrophobic surface, the selectivity ratiois greatly improved and as a result, it is easier to planarize thesurface.

It will be apparent to those skilled in the art that other changes andmodifications may be made in the above-described CMP methods and slurrycompositions without departing from the scope of the invention herein,and it is intended that all matter contained in the above descriptionshall be interpreted in an illustrative and not a limiting sense.

1. A semiconductor device prepared by the sequential steps of: (a)forming on a semiconductor lower layer a first material layer pattern ofa first material which exhibits the property of hydrophobicity withrespect to the slurry composition along a surface of said firstmaterial; (b) forming on said surface of said first material and onadjacent surface of said semiconductor lower layer a second materiallayer of a second material which exhibits the property of hydrophilicitywith respect to the slurry composition along a surface of said secondmaterial; and, (c) performing a chemical mechanical polishing (CMP)process on said surface of said second material using a slurrycomposition consisting essentially of water, abrasive grains selectedfrom the group consisting of silica (SiO2), alumina (Al2O3), ceria(CeO2), magania (Mn2O3), and mixtures thereof, and about 0.001% to about5% by weight of a polymer additive selected from the group consisting ofpoly vinyl methyl ether (PVME), poly ethylene glycol (PEG), polyoxyethylene 23 lauryl ether (POLE), poly propanoic acid (PPA), polyacrylic acid (PAA), poly ether glycol bis ether (PEGBE), and mixturesthereof, wherein the polymer additive improves the selectivity ratio forremoval of the silicon oxide layer relative to removal of thepolysilicon layer.
 2. A semiconductor device prepared in accordance withclaim 1 wherein said slurry composition further consists essentially ofa surfactant and a pH control agent containing acid or base.
 3. Asemiconductor device prepared in accordance with claim 1 wherein the pHof the slurry composition is adjusted to within the range of about 7 to11.
 4. A semiconductor device prepared in accordance with claim 1wherein the concentration of polymer additive ranges from 0.01 % to 1%by weight.
 5. A semiconductor device prepared in accordance with claim 1wherein the selectivity ratio of the slurry composition for removal ofthe silicon oxide layer relative to removal of the polysilicon layer isa minimum of 1.6.
 6. A semiconductor device prepared by the sequentialsteps of: (a) forming on a semiconductor substrate an etch mask patternby depositing on said substrate at least a first material layer of afirst material which exhibits the property of hydrophobicity withrespect to the slurry composition along a surface of said firstmaterial; (b) forming a trench in the semiconductor substrate to apredetermined depth using said etch mask pattern to guide the trenchformation; (c) forming on the structure where said trench has beenformed a second material layer of a second material having theproperties of insularity and exhibiting hydrophilicity with respect tothe slurry composition along a surface of said second material; and, (d)performing a chemical mechanical polishing (CMP) process on said surfaceof said second material so as to expose said surface of said firstmaterial by using a slurry composition consisting essentially of water,abrasive grains selected from the group consisting of silica (SiO2),alumina (Al2O3), ceria (CeO2), magania (Mn2O3), and mixtures thereof,and about 0.001% to about 5% by weight of a polymer additive selectedfrom the group consisting of poly vinyl methyl ether (PVME), polyethylene glycol (PEG), poly oxyethylene 23 lauryl ether (POLE), polypropanoic acid (PPA), poly acrylic acid (PAA), poly ether glycol bisether (PEGBE), and mixtures thereof, wherein the polymer additiveimproves the selectivity ratio for removal of the silicon oxide layerrelative to removal of the polysilicon layer.
 7. A semiconductor deviceprepared in accordance with claim 6 wherein the etch mask patterncomprises a stack layer consisting of said first material layer and ananti-reflective layer.
 8. A semiconductor device prepared in accordancewith claim 6 wherein the method of preparation further comprises thestep of forming a first oxide layer between the semiconductor substrateand the first material layer of the etch mask pattern before carryingout step (a).
 9. A semiconductor device prepared in accordance withclaim 6 wherein the method of preparation further comprises the step offorming a thermal oxide layer on the exposed surface of the trench aftercarrying out step (b) and before carrying our step (c).
 10. Asemiconductor device prepared in accordance with claim 6 wherein themethod of preparation further comprises the step of removing theremaining first material layer after completing step (d).
 11. Asemiconductor device prepared in accordance with claim 6 wherein themethod of preparation further comprises the step of forming asacrificial oxide layer on the semiconductor substrate after the step ofremoving the first material layer.
 12. A semiconductor device preparedin accordance with claim 7 wherein said anti-reflective layer is made ofsilicon oxynitride (SiON).
 13. A semiconductor device prepared inaccordance with claim 6 wherein the concentration of polymer additiveranges from 0.01% to 1% by weight.
 14. A semiconductor device preparedin accordance with claim 6 wherein the selectivity ratio of the slurrycomposition for removal of the silicon oxide layer relative to removalof the polysilicon layer is a minimum of 1.6.
 15. A semiconductor deviceprepared by the sequential steps of: (a) forming on an interlayerinsulating layer of a semiconductor substrate an upper electrode of acapacitor by depositing on said substrate at least a first materiallayer of a first material having the properties of conductivity andexhibiting hydrophobicity with respect to the slurry composition along asurface of said first material; (b) forming on said surface of saidfirst material and on adjacent surface of said semiconductor substrate asecond material layer of a second material which exhibits the propertyof hydrophilicity with respect to the slurry composition along a surfaceof said second material; (c) performing a chemical mechanical polishing(CMP) process on said surface of said second material so as to exposesaid surface of said first material by using a slurry compositionconsisting essentially of water, abrasive grains selected from the groupconsisting of silica (SiO2), alumina (Al2O3), ceria (CeO2), magania(Mn2O3), and mixtures thereof, and about 0.001% to about 5% by weight ofa polymer additive selected from the group consisting of poly vinylmethyl ether (PVME), poly ethylene glycol (PEG), poly oxyethylene 23lauryl ether (POLE), poly propanoic acid (PPA), poly acrylic acid (PAA),poly ether glycol bis ether (PEGBE), and mixtures thereof, wherein thepolymer additive improves the selectivity ratio for removal of thesilicon oxide layer relative to removal of the polysilicon layer; and,(d) forming on the resultant structure a third material layer of a thirdmaterial having the property of insularity.
 16. A semiconductor deviceprepared in accordance with claim 15 wherein said third materialexhibits the property of hydrophilicity with respect to the slurrycomposition along a surface of said third material.
 17. A semiconductordevice prepared in accordance with claim 15 wherein the method ofpreparation further comprises the step of performing a CMP process atleast one time on said surface of said third material in order to exposesaid surface of said first material using said slurry composition.
 18. Asemiconductor device prepared in accordance with claim 15 wherein themethod of preparation further comprises the step of reflowing the thirdmaterial layer under heat after forming said third material layer.
 19. Asemiconductor device prepared in accordance with claim 15 wherein saidfirst material layer is made of polysilicon and said second materiallayer is made of silicon oxide.
 20. A semiconductor device prepared inaccordance with claim 15 wherein a pH control agent containing acid orbase is added to the slurry composition to adjust the pH of the slurrycomposition to within the range of about 7 to
 11. 21. A semiconductordevice prepared in accordance with claim 15 wherein the concentration ofpolymer additive ranges from 0.01% to 1% by weight.
 22. A semiconductordevice prepared in accordance with claim 15 wherein the selectivityratio of the slurry composition for removal of the silicon oxide layerrelative to removal of the polysilicon layer is a minimum of 1.6.